What are used to generate signals of exact frequency are generally called PLL circuits (PLL=phase-locked loop). In a PLL circuit, the frequency of a frequency-generating oscillator is set in such a way that it matches a preset reference frequency such that the phase shift between the output frequency of the frequency-generating oscillator and the reference frequency remains stable or constant. In principle, a distinction can be made between analogue and digital PLL circuits. In the case of digital PLL circuits, which are what will be further considered below, the digital implementation is generally confined to the phase/frequency comparator and to the frequency divider which may be implemented as an option.
The task of the phase/frequency comparator is to compare the frequency of an output-frequency signal from a frequency-generating oscillator in the PLL circuits with the frequency of a preset reference-frequency signal and, if there is a difference, to generate one or more correcting signals which correct the frequency of the output-frequency signal from the frequency-generating oscillator in the PLL circuit in the appropriate way. The way in which a phase/frequency comparator is implemented digitally is generally either in the form of an exclusive-OR gate, an edge-triggered JK flip-flop, or a phase/frequency detector using edge-triggered D flip-flops and resetting logic.
The phase/frequency detector using edge-triggered D flip-flops and resetting logic is a variant digital implementation for phase/frequency comparators that is widely employed because it makes the least demands on the input signals (the exclusive-OR gate requires symmetrical input signals, and the edge-triggered JK flip-flop requires input signals which are not subject to fading).
In the case of the phase/frequency detector using edge-triggered flip-flops and resetting logic, the correcting signal for correcting the frequency of the frequency-generating oscillator comprises, as is known from, for example, Roland E. Best, “Phase Locked Loops”, 3rd edition, McGraw Hill, 1997, ISBN 0-07-006051-7, pages 91-101, two signals, a first signal for the upward correction of the frequency of the frequency-generating oscillator in the event of a positive difference in frequency between the reference frequency and the output frequency, and a second signal for the downward correction of the frequency of the frequency-generating oscillator in the event of a negative difference in frequency between the reference frequency and the output frequency. These two correcting signals are generated by respective edge-triggered D flip-flops which are set by the reference-frequency signal and the output-frequency signal respectively. Because of the phase and frequency relationships which are possible between the reference-frequency signal and the output-frequency signal, there are a total of four possible states for the two D flip-flop outputs (00, 01, 10, 11). Because the last state (11) of the two flip-flop outputs makes no sense (frequency of frequency-generating oscillator to be corrected upward and downward simultaneously), if this state occurs the two flip-flops are reset by means of resetting logic. What is generally used for this purpose is an AND gate whose inputs are connected to the outputs of the two flip-flops and whose output is connected to the resetting inputs of the two flip-flops.
The phase/frequency comparator thus has an asynchronous structure employing feedback, whose behaviour in operation can be characterised as follows: in a phase/frequency detector using edge-triggered D flip-flops, plus resetting logic as above, in the event of a positive difference in frequency (reference frequency fdesired>output frequency factual) the output of the flip-flop which is set by the reference-frequency signal (signal: Correctupward) is set for longer, as a statistical mean, than the flip-flop which is set by the output-frequency signal (signal: Correctdownward). In the event of a negative difference in frequency (reference frequency fdesired<output frequency factual), the output of the flip-flop which is set by the output-frequency signal is set for longer, as a statistical mean, than the flip-flop which is set by the reference-frequency signal. These relationships are shown in FIGS. 1A to 1D for positive and negative differences in frequency fdesired-factual between the reference-frequency signal and the output-frequency signal and for positive and negative differences in phase φdesired-φactual between the two said signals (to make things clearer, the frequency and phase differences that are assumed to exist in the plots are extreme ones).
If a digital phase/frequency comparator of this kind is implemented with programmable logic modules (e.g. FPGA's PAL's, LCA's), the following problems may arise:
Under certain circumstances, the two edge-triggered D flip-flops may not be reset at exactly the same time. The reason for this may be different transit times for the resetting signals due to different lengths of conductor from the resetting logic to the resetting inputs of the edge-triggered D flip-flops, and different resetting times of the two edge-triggered D flip-flops. In the extreme case, an edge-triggered D flip-flop may not be reset at all because, due to appreciable differences in transit time and resetting time, the resetting signal for the edge-triggered D flip-flop which has not yet been reset may have been cancelled again even before the resetting process has been completed due to the resetting of the other edge-triggered D flip-flop. Generally speaking, it is relatively unlikely that circumstances of this kind, and particularly the extreme case which has been described, will occur but, in programmable logic modules, they cannot be ruled out if the placing of the individual logic units is unsatisfactory.
When programming the logic modules, there is generally only a limited amount the user can do to affect the transit times of the individual signals or the resetting times of the flip-flops, which means that if irregularities of this kind occur, the dynamic performance of the PLL circuit can no longer be accurately controlled. Hence there will no longer be a precise deterministic relationship between on the one hand the two correcting signals from the digital phase/frequency comparator and on the other hand the difference in frequency between the reference frequency and the output frequency. This will lead to undesirable jumps in frequency at the output of the frequency-generating oscillator of the PLL circuit and to drifts in phase between the reference frequency and the output frequency. These system deviations on the part of the phase/frequency-locked loop, which appreciably reduce the quality of the control performed by the PLL circuit, cannot generally be corrected and in the extreme case may cause instability on the part of the control loop.